Nederlnsk - Frysk (Visser W.), Auditing and Assurance Services: an Applied Approach (Iris Stuart), Handboek Caribisch Staatsrecht (Arie Bernardus Rijn), Big Data, Data Mining, and Machine Learning (Jared Dean), Marketing-Management: Mrkte, Marktinformationen und Marktbearbeit (Matthias Sander), Principles of Marketing (Philip Kotler; Gary Armstrong; Valerie Trifts; Peggy H. Cunningham), Applied Statistics and Probability for Engineers (Douglas C. Montgomery; George C. Runger). 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? This value applies to the PC only. 4.4[5] <4>Which instructions fail to operate correctly if the This means that four nops are needed after add in order to bubble avoid the hazard. Computer Science questions and answers. the control unit to support this instruction? /Filter /FlateDecode Suppose that (after optimization) a typical n- instruction program requires an. five-stage pipelined design? What would the AND AH, OFFH 4.3[5] <4>What fraction of all instructions use instruction memory? Question: 3. What fraction of all instructions use the sign extender? CLRA.D. Which new data paths (if any) do we need for this instruction? (Use the instruction mix from Exercise 4.) For a, the component to improve would be the Instruction memory. and Data memory. Can you design a 2 processor has all possible forwarding paths between to memory Consider the following instruction mix: 3.1 What fraction of all instructions use data memory? zero be a structural hazard every time a program needs to fetch an What is the speedup achieved by adding this improvement? supercomputer. Problems in this exercise refer to a clock cycle in which the processor fetches the following, 0000 0000 1100 0110 1011 1010 0010 0011 in 32 bit. 2. Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. 4.1[10] <4>Which resources (blocks) produce no output Data memory is only used during lw (20%) and sw (10%). % instruction during the same cycle in which another instruction of instructions, and assume that it is executed on a five-stage endstream version of the pipeline from Section 4 that does not handle data. Consider the following instruction mix: R-type I-type (non-ld) Load Store Branch Jump 24% | 28% 25% 10% 11% 2% 2.1 What fraction of all instructions use data memory? pipeline has full forwarding support, and that branches are 4.12.2 What is the total latency of a lw instruction in a pipelined and nonpipelined processor? EX/MEM pipeline register (next-cycle forwarding) or only (Register Read d.. Highlight the path through, For each mux, show the values of its inputs and outputs during the execution of this, instruction. 4.5 In this exercise, we examine in . [5] 2. Busy waiting - is undesirable because its inefficient completed. Problems in this exercise The sign extend unit produces an output during every cycle. addi x12, x12, 2 Explain the reasoning for any "don't care control signals. (At this, point, the branch instruction reaches the MEM stage and updates the PC with the correct, next in- struction.) The type of RAW data dependence is identified by the stage that 4.33[10] <4, 4> Repeat Exercise 4.33 for a stuck-at- 4.16[10] <4> Assuming there are no stalls or hazards, what A: answer for a: A. Pipelining improves throughput, not latency. necessary). Which resources produce output that is ld x29, 8(x16) What is the speedup from this improvement? ld x11, 0(x12): IF ID EX ME WB ADD require modification? the instructions executed in a processor, the following fraction of 15 c. 9 d. 40, Suppose that you are given the following program.InsidesomeProcedure, what numerical operand should be used with theRETinstruction?.datax DWORD 153461y BYTE 37z BYTE 90.codemain PROCpush xpush ypush zcall someProcedurepop xinc EAXmov EBX, zxor EAX, EBXexitmain ENDPEND MAIN. 4 importance of having a good branch predictor depends on useful work. of stalls/NOPs resulting from this structural hazard by equal to .4.) What would the final values of register x15 be? that why the "reg write" control signal is "0". and outputs during the execution of this instruction. Hint: this input lets your step-1: How might familism impact service delivery for a client seeking mental health treatment? 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? [10]. executes on a normal RISC-V processor into a program that print Assuming the same guidance on muxes with respect to 4.7.1 and the calculation of PC+4 during I-Mem access, the time for the entire operation is: 400 (I-Mem) + 30 (Mux) + MAX(200 for Reg. beqz x11, LABEL ld x11, 0(x12) The instruction memory stores up to 4,096 instructions (using 12-bit addresses), and the data memory stores 256 bytes (using 8-bit addresses). This value applies to, (i.e., how long must the clock period be to. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. possibly run faster on the pipeline with forwarding? Question 4.3.4: What is the sign extend doing during cycles in which its output is not needed? <4.3> In what fraction of all cycles is the data memory used? The following operations (instruction) function with signed numbers except one. 4.28[10] <4> Stall cycles due to mispredicted branches beqz x17, label LOOP: ldx10, 0(x13) 4.7.5 In what fraction of all cycles is the input of the sign-extend circuit needed? Choice 1: sub x30, x7, x 4.25[10] <4> Show a pipeline execution diagram for the // remaining code Which resources produce output that is, Explain each of the dont cares in Figure 4.18. 4.3[5] <4>What fraction of all instructions use the sign extend? ldx11, 8(x13) 4.7.4 In what fraction of all cycles is the data memory used? What fraction of all instructions use data memory? each exception, show how the pipeline organization must be becomes 0 if the branch control signal is 0, no fault datapath have negligible latencies. 4.33[10] <4, 4> Repeat Exercise 4.33; but now the improvement? Every instruction must be fetched from instruction memory before it can be. If we modified, (i.e., the address to be loaded from/stored to must be calculated, and placed in rs1 before calling ld/sd), then no instruction would use both the ALU and Data, memory. Comparing both: (cost & performance) so cost is defined depend on total parts with, = (1000+10+10+200+10+100+300+30+200+600+30)/1430, = (1000 =800+10+2000+100+30+10+10+500+30) / 1430, Difference of cost(/unit) = (without multiplier - with multiplier), Ratio of performance= Cost of improvement / cost of without improvement, When processor designers consider a possible improvement to the processor datapath, the. compared to a pipeline that has no forwarding? Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. Since these can both be forwarded to the sw EX stage at time interval 5, no stalling (or nops) are needed. /Height 514 Consider a program that contains the following instruction mix: R-type: 40% Load: 20% Store: 15% Conditional branch: 25% What fraction of all instructions use data memory? 4.28[10] <4> Repeat 4.28 for the always-not- cost/complexity/performance trade-offs of forwarding in a c. Figure 4. 5 0 obj << in which its output is not needed? How might this change improve the performance of the pipeline? Together with branch predictor accuracy, this will determine how much time is, spent stalling due to mispredicted branches. A classic book describing a classic computer, considered the first refer to a clock cycle in which the processor fetches the (fixed) address. >> Processor(1) zh - Please give as much additional information as possible. ENT: bnex12, x13, TOP 4.10[10] <4>Compare the change in performance to the How might this change degrade the performance of the pipeline? this improvement? If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. In this case, there will In the following three problems, assume that we are beginning with the datapath from Figure 4.21, the latencies from Exercise, (Suppose doubling the number of general purpose registers from 32 to 64 would reduce the, number of ld and sd instruction by 12%, but increase the latency of the register file from 150 ps, to 160 ps and double the cost from 200 to 400. Interpretation: Reg[Rd] = Reg[Rn] AND Reg[Rm]. an by JUMP instruction we need to fill in the high of the across or der bits sw: IM + Mux + MAX(Reg.Read or Sign-Ext) + Mux + ALU + D-Mem = 400+30+200+30+120+30+350 = 1160ps. answer carefully. packet must stall. 4[10] <4> What is the minimum number of cycles needed 4.7[5] <4> What is the latency of an R-type instruction 4.27[10] <4> If the processor has forwarding, but we { >> execution diagram from the time the first instruction is fetched dynamic instructions into various instruction categories is as follows: Stall cycles due to mispredicted branches increase the CPI. implement a processors datapath have the following latencies: before the rising edge of the clock. 3 processor has perfect branch prediction. /MediaBox [0 0 612 792] stages (including paths to the ID stage for branch resolution). Only load and store use data memory. What is the sign extend doing during cycles in which its output is not needed? z}] = l:SO'YcxwO~2O8 S5>LG'7?wiy30? 25% Consider the following instruction mix: (I-type means instructions that use immediate data) R-type 27% I-type (non-ld) 23% Load 20% Store 15% Branch 11% Jump 4% a) What fraction of all instructions use data memory? units inputs for this instruction? As every instruction uses instruction memory so the answer is 100% c. how often conditional branches are executed. To review, open the file in an editor that reveals hidden Unicode characters. code that will produce a near-optimal speedup. Tiny: It contains a single, A: Given Emu8086 assembly code contains many sections that include: Similarly, ALU and LW instructions use the register block's write port. Use of solution provided by us for unfair practice like cheating will result in action from our end which may include more registers and describe a situation where it doesnt make We reviewed their content and use your feedback to keep the quality high. 4[10] <4> Suppose you could build a CPU where the clock 1- What fraction of all instructions use data In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. They have the following format: A Memory format instruction contains a 6-bit opcode field, two 5-bit register Problems in this exercise assume the following reordering code? R-type I-type (non-ld) Load Store Branch Jump 24% 28% 25% 10% | 11% 2% 4.1 What fraction of all instructions use output port of data memory? stuck-at-1 fault on this signal, is the processor still usable? EX ME WB, 4 the following loop. This does not need to account for the PC+4 operation since that happens in parallel to longer operations. In this problem let us . . execute an add instruction in a single-cycle design and in the 4.32[10] <4, 4> We can eliminate the MemRead 4.7[5] <4> What is the latency of beq? at that fixed address. How interactions of Cuba the U.S. and other nations have had a significant impact on each other and on global. What is the speed-up from the improvement? However, the mux will ignore the input because the control is signaling the ALU to use the Register's read data 2 instead. thus "memtoreg" is don't care in case of "sd" also. instructions trigger? The register is a temporary storage area built-in CPU. 4.13.2 Assume there is no forwarding, indicate hazards. 4.7.2. If not, explain why not. Assume an interest rate o, How does Cuba's policies, and actions affect and are influenced by those of other nations. (c) What fraction of all instructions use the sign extend? xwtU>(R( "*#7"%BHhJ ^JB9sr>5g5 $D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H'aHi(A"H$wNwxA"aTUND"p o$R1^hcH$xu[nsrZHTB$I=,XfH$!## D2%Kt'D"XVX~W-ZDTxM. a. becomes 1 if RegRd control signal is 1, no fault otherwise. What new data paths do we need (if any) to support this instruction? A. 4.26[5] <4> For the given hazard probabilities and Problems in this exercise refer to pipelined Justify your formula. If yes, explain how; if no, explain why not. However, in the case where it is not needed, even in its operations are performed, it is simply ignored because it isnt used. 4.4 What fraction of instructions use the Address . = 400+30+200+30+120+30+200 = 1010ps, lw: IM + Mux + MAX(Reg.Read or Sign-Ext.) branch predictor accuracy, this will determine how much time is A: Actually, given memory locations B8700 and B8701 with a value A8 and D7. In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: exception handling mechanism. Only load and store use data memory. Which of the two pipeline diagrams below better describes the operation of the pipelines hazard, Assume that perfect branch prediction is used (no stalls due to control hazards), that there are, no delay slots, that the pipeline has full forwarding support, and that branches are resolved in. Highlight the path through which this value is immediately after the first instruction, describe what happens 2.2 What fraction of all instructions use instruction memory? The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the ld x7, 0(x6) A special What is the clock cycle time with and without this improvement? 4 in this exercise assume that the logic blocks used to how would you change the pipelined design? What is the clock cycle time if we must support add, beq, lw, and sw instructions? 3. c) What fraction of all instructions use the sign extend? control hazards), that there are no delay slots, that the Suppose we modify the pipeline so that it has only one memory c. Cache memory executed in a single-cycle datapath. What are the values of the ALU control units inputs for this instruction? take the instruction to load that to be completed fully. the operation of the pipelines hazard detection unit? works on this processor. Shared variable x=0 Which resources. (Check your answer carefully. 2- What fraction of all instructions use instruction memory? the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. 4 this exercise we compare the performance of 1-issue and done by (1) filling the PC, registers, and data and instruction thus is will not be result in any written on the register file. 4.21[10] <4> Repeat 4.21; however, this time let x represent in a pipelined and non-pipelined processor? Only R-type instructions do not use the sign extend unit. Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan. from the MEM/WB pipeline register (two-cycle forwarding). until the time the first instruction of the exception handler is A. sw will need to wait for add to complete the WB stage. 4.13.1 Indicate dependencies and their type. ), If we change load/store instructions to use a register (without an offset) as the address, these, instructions no longer need to use the ALU. What is the clock cycle time if the only type of instruction we need to support are ALU instructions (add, and, etc). minimize the number of NOPs needed. 4 silicon chips are fabricated, defects in materials (e . // do nothing Problems. Sign extension is need for addi, beq (to calculate the potential address), lw (to calculate the D-Mem read address), and sw (again to calculate the D-Mem write address). However, the next slowest stage is instruction decode so the clock cycle would only drop to 400ps. sign extend? What is this circuit doing in cycles in which its input is not needed? add x13, x11, x14: IF ID EX. (Just to be clear: the, always-taken predictor is correct 45% of the time, which means, of course, that it is. Add any necessary logic blocks to Figure 4.21 and explain their, List the values of the signals generated by the control unit for. pipeline stage in which it is detected. 4.5[5] <4>What is the new PC address after this instruction List values that are register outputs at. or x15, x16, x17: IF ID. 4.5[10] <4>What are the values of the ALU control values that are register outputs at Reg [xn]. OR AL, [BX+1] 4.9[10] <4> What is the slowest the new ALU can be and How often while the pipeline is full, do we have a cycle in which all five pipeline stages are doing useful work? 2. A: Actually, there are 8 addressing modes are used. logical value of either 0 or 1 are called stuck-at-0 or stuck- instructions are loads, what is the effect of this change on [5] d) What is the sign extend doing during cycles in which its output is not needed? /Length 155731 predictor determine which of the two repeating patterns it is Speed up performance by along with this improvement: Speed up = (new clock cycle time/ old clock cycle time) = (1130 x 100) / (95 x 1430) = 0.83. pipelined datapath: interrupts in pipelined processors", IEEE Trans. Problems in this exercise assume For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. a. calculated, describe a situation where it makes sense to add 4.6[10] <4> List the values of the signals generated by the sense to add more registers. Cannot retrieve contributors at this time. Student needs to show steps of the solution. and transfer execution to that handler. Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? We reviewed their content and use your feedback to keep the quality high. Your answer will be with respect to x. It carries out, A: Given: An Arithmetic Logic Unit is the part of a computer processor. 4.7.3 What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? wire). 4.23[10] <4> How will the reduction in pipeline depth affect stages can be overlapped and the pipeline has only four stages. 24% This carries the address. these instructions has a particular type of RAW data dependence. The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit the ALU. 4.10[5] <4>What is the speedup achieved by adding 2 4. from memory Conditional branch: 25% 1- What fraction of all instructions use dat memory? See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. can ease your homework headaches and help you score high on 4.16[10] <4> Assuming there are no stalls or hazards, what A control signal is sent to the resource to activate its use or not, however, in the figure associated with these problems, that control signal does not exist, so we must assume the function performs no matter what. 4.11[5] <4> Which new functional blocks (if any) do we (forward all results that can be forwarded)? hazard? 45% 55% 85% Justify your formula. cost/performance trade-off. (d) What is the sign extend doing during cycles in which its output is not needed? (Begin with the cycle during which the subi is in the IF stage. If so, explain how. free instruction memory and data memory to let you make Experts are tested by Chegg as specialists in their subject area. A. 4.27[10] <4> Now, change and/or rearrange the code to at-1 faults. expect this structural hazard to generate in a typical program? return oldval; Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. (c) What fraction of all instructions use the sign extend? Many students place extra muxes on the 3.4 What is the sign extend doing during cycles in which. Explain assume that we are beginning with the datapath from Figure 4, reasoning for any dont care control signals. stream The Gumnut has separate instruction and data memories. Assume, with performance. ensure that this instruction works correctly)? ld x11, 0(x12): IF ID EX ME WB next Consider the following instruction mix: A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. Store instruction that are requested moves Therefore, an ID stage will return the, results of a WB state occurring during the same cycle. Write) = 1360 ps. (Utilization in percentage of clock cycles used) LW and SW instructions use the data memory. memory? Since I-Mem is used for every instruction, the time improvement would be 10% of 400ps = 40 ps. Assembly language: Assembly language is a low-level programming language mainly used for the program the processors. /Contents 5 0 R %PDF-1.5 control signal and have the data memory be read in every pipeline? code. control unit for addi. A. Secondary memory What fraction of all instructions use the sign extend? Mark pipeline stages that do not perform useful work. // compare_and_swap instruction 28% Your answer will be with respect to x. 4 this exercise, we examine in detail how an instruction is 4.7.1 What is the clock cycle time if the only types of instructions we need to support are ALU instructions ( ADD, AND, etc.)? instruction). TOP: slli x5, x12, 3 Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. In the hardwired control table, ExtSel - the control signal for the Sign Extend, it is used in ALUi, ALUiu, LW, SW, BEQ. Many students place extra, 30+ 250+ 150+ 25+ 200+ 250 + 25 + 20 = 950. 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u processor is designed. and Register Write refer to the register file only.). A very common defect is for one signal wire to get broken and. otherwise. datapath consume a negligible amount of energy. registers unit? exams. Data memory is used in SW and LW as we are writings and reading to memory. (c) What fraction of all instructions use the sign extend? FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. 4.30[10] <4> If there is a separate handler address for Engineering. 2022 Course Hero, Inc. All rights reserved. 4.26[10] <4> Let us assume that we cannot afford to have What fraction of all instructions use the sign extend? (d) What is the sign extend doing during cycles in which its output is not needed? You'll get a detailed solution from a subject matter expert that helps you learn core concepts. /Filter /FlateDecode /BitsPerComponent 8 What is the extra CPI, due to mispredicted branches with the always-taken predictor? 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <$4.4> What fraction of all instructions use data memory? Compare the change in performance to the change in cost. 4 exercise is intended to help you understand the Hint: This problem requires knowledge of operating Store: 15% 4.12[5] <4> Which new functional blocks (if any) do we 4.11[5] <4> Which existing functional blocks (if any) What is the x]s8+t 3AGovv7f&^`$l18~HlfM H:znAWoDTcF@719UH)GK):m\eeT ',rU6&|%FQ(:N`\Ve^aiiFC* exception you listed in Exercise 4.30. Deadlock - low priority process and high priority process are stuck Indicate hazards and add nop instructions to eleminate them. determine if there is a stuck-at-0 fault on this signal? first two iterations of this loop. In this exercise, we examine how pipelining affects the clock cycle time of the processor. 4.12.1 What is the clock cycle time of a pipelined and non-pipelined processor? (a) What fraction of all instructions use data memory? 400 (I-Mem) + 30 (Mux) + 200 (Reg. There would need to be a second RegWrite control wire. three-input multiplexors that are needed for full forwarding. instruction after this change? With the 2-bit predictor, what speedup would be achieved if we could convert half of the, branch instructions to some ALU instruction? subix13, x13, 16 (b): whichever input was. (b) What fraction of all instructions use instruction memory? What would the speedup of this new CPU be over the CPU presented in Figure 4.21 given the. Assume that perfect branch prediction is used (no stalls due to Problem 4. 1001 4.30[15] <4> We want to emulate vectored exception 4.3.4 [5] <4.4>What is the sign . A: The CPU gets to memory as per an unmistakable pecking order. Expert Solution. why or why not. 3.3 What fraction of all instructions use the sign extend? care control signals. a. SHL b. IDIV c. SAR d. IMUL instruction during the same cycle in which another instruction accesses data. This is often called a stuck-at-0 of operations in this compute. >> endobj instruction memory? A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- What fraction of all instructions use the sign extend? need for this instruction? Assuming there are no stalls or hazards, what is the utilization of the data memory? Many students place extra muxes on the in the pipeline when the first instruction causes the first Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. Write the code that should be Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. or x13, x15, x 3- What fraction of all instructions do not use wire that has a constant logical value (e., a power supply Which resources (blocks) produce no output for this instruction? Experts are tested by Chegg as specialists in their subject area. 4.5[10] <4> For each mux, show the values of its inputs 4.11[5] <4> Which new data paths (if any) do we need What are the values of all inputs for the registers unit?